1. 6G, VCO for GSM receiver with -140dBc phase noise at 450mW power.
2. 10GSps 12-bit Nyquist RF DAC with dynamic element matching and 83dB SFDR

Worked on a number of high performance industrial strength designs including a open loop scheme to deliver high frequency current for power amplifier in envelope tracking, a gm-C loop filter for lower power and higher linearity in second order delta sigma ADC to attain an SNDR of 120dB in audio band, a high bandwidth and dc gain feed forward chopped opamp architecture for attaining low input referred offset of 20uV and a low power 1MHz FLL with +/- 4% accuracy to provide clock in sleep mode.

Design of low power high speed voltage regulator for memory at 720mV power supply.

Design of chopper stabilization in discrete time delta sigma modulators.