Prospective Students | Rakesh IIT Delhi :: Dr. Rakesh Kumar Palani

1. Development of Signal Processing chip for GNSS Anti-Jamming functionality

The primary objective of the proposed research is to explore the design of a high resolution hybrid ADC. While Sigma delta ADCs were used to achieve high SFDR, there are inherently limited by the oversampling ratio. On the other hand, Nyquist rate converters suffer from mismatch and they require a huge digital calibration engine. In this project we will try to explore design without heavy digital background calibration.

2. Electronic sub-system design for RADARs and LASERs" as I-Hub Foundation for COBOTICS”

This project is aimed to build a transceiver for Radar application. This can be used in drone system in relation to cobotics and for proximity sensor and localization. The transmitter will be built in a custom design integrated circuit to realize compact RADAR.

1. DST-NQM-Quamtum Computing Hub-Technical Group (TG)

Design and development of IPs for qubit controller at cryogenic temperature

2. Analog FE for High Dynamic Range CMOIS sensor

3. Design of low Jitter Frequency Synthesizer for Radar Applications

The project targets high-performance analog-to-digital conversion under clock jitter constraints. It proposes a delta-sigma sampling architecture with low oversampling to shape jitter noise out of band, effectively reducing its impact. An analog passive switched-capacitor filter then removes out-of-band noise, followed by down-conversion to Nyquist rate and digitization using Nyquist time-interleaved ADCs. This method avoids typical timing errors and provides anti-aliasing filtering for free, enabling robust digital conversion of wideband signals for software-defined radios and military sensors.

1. Design of Charge Recycling ternary RF DAC based transmitter for software defined Radios, Core Research Grant (CRG), Science and Engineering Board (SERB)

This project is aimed at developing a digitally intensive Radio Frequency Digital to Analog Converter (RF-DAC) based transmitter .The proposed RF DAC is a ternary DAC unlike conventional binary DACs which will recycle excess charge back to the supply. As the spectral purity and bandwidth available for each channel is limited by the performance of the DAC, various methods like calibration and noise-shaping have been proposed thus far.

2. Design of Wide band PLL”, Sponsored by Mixed Signal Devices Inc, Irvine CA

This project is aimed at designing a wide band fractional N PLL with a novel charge pump architecture. Preliminary results show the mismatch of 0.01% current mismatch in charge pump.

3. Design of high speed high resolution DACs”, IIT Delhi New faculty startup seed grant

The demand for high quality and high speed data rata in communication systems keeps increasing. Complex digital signal processing is made feasible by technology scaling. However, the spectral purity and speed is limited by Digital to Analog (DAC) Converters. The digital assisted analog approach is taken by several researchers in literature to solve this issue. However, these attempts are often limited with resolution of calibrating circuit or increase in noise floor. This project is aimed at increasing the resolution and speed of these DACs by using various digital algorithms and segmentation techniques.

4. Compact, high efficiency transmitters with power efficient Power Amplifiers for Satellite-Borne Communication Systems, FIRP in collaboration with Prof Kirti Dhwaj, CARE IITD

This project is aimed to develop an RF Transmitter with high speed DAC that can deliver data with high carrier frequency. Gain programmability will be incorporated in the transmitter to compensate for the Power amplifier gain variation.

Projects